The SONET system is intended for implementing the electronic/photonic interface for fiber optic communication networks according to the new Synchronous Optical Network (SONET) Standard defined in ANSI Standard T1.105 etc. According to the SONET Standard, electronic signals are formatted in synchronous transport signal (STS) frames of 810 bytes with 125 .mu.S frame time period and base transmission rate of 51.840 Mb/s. The STS frames include the transport overhead bytes and a synchronous payload envelope (SPE) of data bytes combined in a standard frame format of 9 rows of bytes by 90 columns of bytes. The basic SONET STS-1 frame is constructed with three columns of transport overhead bytes as the first three columns followed by 87 columns of SPE data bytes. Each row is therefore composed of 3 transport overhead bytes and 87 data bytes. The SPE also includes one column of path overhead bytes.
Within each STS frame the synchronous payload envelope (SPE) may be composed of so called virtual tributaries (VT's), i.e., data structures from lower speed or lower frequency service networks. The VT's are packaged or multiplexed together in the synchronous payload envelopes of STS frames for high speed SONET transmission. Multiple STS frames can also be multiplexed together in a single STS-N frame structure.
Internationally, the SONET system is referred to as synchronous digital hierarchy or SDH. The basic SDH frame is similar to an STS-3 frame of 9 rows by 270 columns. The rows are divided into an initial 9 columns of transport overhead bytes followed by 261 columns of data bytes. Each row is therefore composed of 9 transport overhead bytes followed by 261 data bytes.
In summary, SONET ANSI T1 sets the standard for the formatting of data into frames of transport overhead bytes and data payload envelopes, the multiplexing of formatted data, processing of frames, scrambling of data for power modulation, and generally the data handling and management for interfacing electronic signals with optical carriers on fiber optic transmission networks.
Referring to FIG. 1, a typical pointer processor circuit consists of a pointer interpreter (PI), first in first out memory (FIFO) and a pointer generator (PG). The PI circuit receives an incoming frame, locates the pointer in the transport overhead bytes of the incoming frame identified as the H1 H2 bytes, and interprets the pointer which points to and gives the location of the trace byte J1. J1 identifies the start of the synchronous payload envelope of data bytes for that incoming frame. The PI then writes the data bytes of the incoming frame to the FIFO.
The pointer generator constructs a new pointer H1 H2 because generally the data payload envelope of data bytes will begin at a different location of the synchronous payload envelope in the outgoing frame compared to the incoming frame. The incoming and outgoing frames are independent of each other. The pointer generator circuit also reads the data bytes from the FIFO and begins constructing a new SONET frame as the outgoing frame.
The pointer processor of the present invention including the PI, FIFO, and PG is part of the overall SONET/SDH frame processing circuit. For example the PI is coupled on the upstream side to a frame detector circuit for detecting overhead bytes from the incoming frame. This circuit checks the incoming framing bytes A1A2 and other overhead bytes. Transport overhead bytes are extracted from the circuit and parity bytes are checked.
The PG circuit is coupled to a multiplexing circuit or MUX followed by an overhead insertion circuit for restoring new transport overhead bytes to the outgoing frame. The multiplexer or MUX constructs the frame according to a STS-N formula, parity bits are inserted, and finally the bits are modulated by a feedback scrambler. It is noted that feedback scrambling is not for the purpose of encryption but for modulating power by distributing pulse signal edges.
The SONET STS frames themselves can be multiplexed into N frame structures. For example a 3 to 1 multiplexer will combine 3 STS-1 frames into a single STS-3 frame as illustrated in FIG. 1A. Synchronous multiplexing is achieved by interleaving bytes at corresponding locations of the respective STS frames after aligning the transport overhead bytes of the respective STS frames. A multiplexed STS-N frame has the same frame time period of 125 .mu.S as an STS-1 frame. The SONET Standard accommodates byte interleaved synchronous multiplexing STS-N of at least 48 STS frames. An STS-48 frame results in SONET Signal transmission rates in the 2 gHz range (e.g. 48.times.51.840 Mb/s).
A typical SONET/SDH pointer processor consists of a pointer interpreter (PI), a first in first out memory (FIFO) and a pointer generator (PG) as illustrated in FIG. 1. The PI block receives the incoming frame, interprets the pointer bytes, and counts down to the first byte of the payload. The first data byte of the payload is identified by the J1 byte or trace byte. This byte is tagged and sent through the FIFO. When this byte is received in the PG block, the new pointer is calculated based on when this tagged byte arrives relative to the outgoing frame.
For instance if the incoming frame has a pointer value of 400, then the payload bytes are counted until the 400th byte is being sent through the FIFO starting at the byte following the H3 byte per SONET/SDH standards. This byte which is the J1 path overhead trace byte, would be tagged. If this tagged byte is received by the PG block when the 10th payload byte of the next outgoing frame is being processed, then the pointer in the next frame will be 10. The delay in counting down the bytes to the start of the payload in the PI block, can lead to a two-frame delay in changing pointers on the outgoing frame.